/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

/** *****************************************************************************************************
 *  \file     Wdg_Reg.h                                                                                 *
 *  \brief    This file contains interface header for WDG MCAL driver, ...                              *
 *                                                                                                      *
 * <table>                                                                                              *
 * <tr><th>Date           <th>Version                                                                   *
 * <tr><td>2023/07/17     <td>1.0.0                                                                     *
 * </table>                                                                                             *
 *******************************************************************************************************/

#ifndef WDG_REG_H
#define WDG_REG_H

/********************************************************************************************************
 *                                 Global Macro definition                                              *
 *******************************************************************************************************/

/** \brief Driver Implementation Major Version */
#define WDG_REG_H_SW_MAJOR_VERSION    1
/** \brief Driver Implementation Minor Version */
#define WDG_REG_H_SW_MINOR_VERSION    0
/** \brief Driver Implementation Patch Version */
#define WDG_REG_H_SW_PATCH_VERSION    0
/* @} */
/**
 *  \brief WDG Driver Module Register  Bit Width INFO
 *
 *  Defines for  Bit Width INFO define
 *  @{
 */
/** \brief Driver function 1 bit width */
#define WDT_1BIT_WIDTH                 (0x1U)
/** \brief Driver function 2 bit width */
#define WDT_2BIT_WIDTH                 (0x2U)
/** \brief Driver function 3 bit width */
#define WDT_3BIT_WIDTH                 (0x3U)
/** \brief Driver function 4 bit width */
#define WDT_4BIT_WIDTH                 (0x4U)
/** \brief Driver function 8 bit width */
#define WDT_8BIT_WIDTH                 (0x8U)
/** \brief Driver function 16 bit width */
#define WDT_16BIT_WIDTH                (16U)
/** \brief Driver function 0 bit offset */
#define WDT_0BIT_OFFSET                (0x0U)
/** \brief Driver function 1 bit offset */
#define WDT_1BIT_OFFSET                (0x1U)
/** \brief Driver function 2 bit offset */
#define WDT_2BIT_OFFSET                (0x2U)
/** \brief Driver function 3 bit offset */
#define WDT_3BIT_OFFSET                (0x3U)
/** \brief Driver function 6 bit offset */
#define WDT_6BIT_OFFSET                (0x6U)
/** \brief Driver function 16 bit offset */
#define WDT_16BIT_OFFSET                (16U)
/** \brief Driver function 28 bit offset */
#define WDT_28BIT_OFFSET                (28U)

#define WDT_CTRL_OFF  0x0U

#define FM_WDT_CTRL_PRE_DIV_NUM  ((uint32)0xffffU << 16U)
#define FV_WDT_CTRL_PRE_DIV_NUM(v) \
  (((uint32)(v) << 16U) & FM_WDT_CTRL_PRE_DIV_NUM)
#define GFV_WDT_CTRL_PRE_DIV_NUM(v) \
  (((uint32)(v) & FM_WDT_CTRL_PRE_DIV_NUM) >> 16U)

#define BM_WDT_CTRL_WDT_EN_STA  ((uint32)0x01U << 10U)

#define BM_WDT_CTRL_SELFTEST_TRIG  ((uint32)0x01U << 9U)

#define BM_WDT_CTRL_WDT_EN_SRC  ((uint32)0x01U << 8U)

#define BM_WDT_CTRL_DBG_HALT_EN  ((uint32)0x01U << 7U)

#define BM_WDT_CTRL_AUTO_RESTART  ((uint32)0x01U << 6U)

#define BM_WDT_CTRL_WTC_SRC  ((uint32)0x01U << 5U)

#define FM_WDT_CTRL_CLK_SRC  ((uint32)0x7U << 2U)
#define FV_WDT_CTRL_CLK_SRC(v) \
  (((uint32)(v) << 2U) & FM_WDT_CTRL_CLK_SRC)
#define GFV_WDT_CTRL_CLK_SRC(v) \
  (((uint32)(v) & FM_WDT_CTRL_CLK_SRC) >> 2U)

#define BM_WDT_CTRL_WDT_EN  ((uint32)0x01U << 1U)

#define BM_WDT_CTRL_SOFT_RST  ((uint32)0x01U << 0U)

#define WDT_WTC_OFF  0x4U

#define FM_WDT_WTC_WTC_VAL  ((uint32)0xffffffffU << 0U)
#define FV_WDT_WTC_WTC_VAL(v) \
  (((uint32)(v) << 0U) & FM_WDT_WTC_WTC_VAL)
#define GFV_WDT_WTC_WTC_VAL(v) \
  (((uint32)(v) & FM_WDT_WTC_WTC_VAL) >> 0U)

#define WDT_WRC_CTL_OFF  0x8U

#define BM_WDT_WRC_CTL_REFR_TRIG  ((uint32)0x01U << 3U)

#define BM_WDT_WRC_CTL_SEQ_REFR_EN  ((uint32)0x01U << 2U)

#define BM_WDT_WRC_CTL_MODE1_EN  ((uint32)0x01U << 1U)

#define BM_WDT_WRC_CTL_MODE0_EN  ((uint32)0x01U << 0U)

#define WDT_WRC_VAL_OFF  0xcU

#define FM_WDT_WRC_VAL_WIN_LOW_LIMIT  ((uint32)0xffffffffU << 0U)
#define FV_WDT_WRC_VAL_WIN_LOW_LIMIT(v) \
  (((uint32)(v) << 0U) & FM_WDT_WRC_VAL_WIN_LOW_LIMIT)
#define GFV_WDT_WRC_VAL_WIN_LOW_LIMIT(v) \
  (((uint32)(v) & FM_WDT_WRC_VAL_WIN_LOW_LIMIT) >> 0U)

#define WDT_WRC_SEQ_OFF  0x10U

#define FM_WDT_WRC_SEQ_SEQ_DELTA  ((uint32)0xffffffffU << 0U)
#define FV_WDT_WRC_SEQ_SEQ_DELTA(v) \
  (((uint32)(v) << 0U) & FM_WDT_WRC_SEQ_SEQ_DELTA)
#define GFV_WDT_WRC_SEQ_SEQ_DELTA(v) \
  (((uint32)(v) & FM_WDT_WRC_SEQ_SEQ_DELTA) >> 0U)

#define WDT_RST_CTL_OFF  0x14U

#define FM_WDT_RST_CTL_RST_CNT_SHIFTER  ((uint32)0xfU << 28U)
#define FV_WDT_RST_CTL_RST_CNT_SHIFTER(v) \
  (((uint32)(v) << 28U) & FM_WDT_RST_CTL_RST_CNT_SHIFTER)
#define GFV_WDT_RST_CTL_RST_CNT_SHIFTER(v) \
  (((uint32)(v) & FM_WDT_RST_CTL_RST_CNT_SHIFTER) >> 28U)

#define FM_WDT_RST_CTL_RST_WIN  ((uint32)0xffU << 20U)
#define FV_WDT_RST_CTL_RST_WIN(v) \
  (((uint32)(v) << 20U) & FM_WDT_RST_CTL_RST_WIN)
#define GFV_WDT_RST_CTL_RST_WIN(v) \
  (((uint32)(v) & FM_WDT_RST_CTL_RST_WIN) >> 20U)

#define BM_WDT_RST_CTL_WDT_RST_EN  ((uint32)0x01U << 18U)

#define BM_WDT_RST_CTL_INT_RST_MODE  ((uint32)0x01U << 17U)

#define BM_WDT_RST_CTL_INT_RST_EN  ((uint32)0x01U << 16U)

#define FM_WDT_RST_CTL_RST_CNT  ((uint32)0xffffU << 0U)
#define FV_WDT_RST_CTL_RST_CNT(v) \
  (((uint32)(v) << 0U) & FM_WDT_RST_CTL_RST_CNT)
#define GFV_WDT_RST_CTL_RST_CNT(v) \
  (((uint32)(v) & FM_WDT_RST_CTL_RST_CNT) >> 0U)

#define WDT_EXT_RST_CTL_OFF  0x18U

#define BM_WDT_EXT_RST_CTL_RST_REQ_POL  ((uint32)0x01U << 28U)

#define FM_WDT_EXT_RST_CTL_RST_WIN  ((uint32)0xffU << 20U)
#define FV_WDT_EXT_RST_CTL_RST_WIN(v) \
  (((uint32)(v) << 20U) & FM_WDT_EXT_RST_CTL_RST_WIN)
#define GFV_WDT_EXT_RST_CTL_RST_WIN(v) \
  (((uint32)(v) & FM_WDT_EXT_RST_CTL_RST_WIN) >> 20U)

#define BM_WDT_EXT_RST_CTL_EXT_RST_MODE  ((uint32)0x01U << 17U)

#define BM_WDT_EXT_RST_CTL_EXT_RST_EN  ((uint32)0x01U << 16U)

#define FM_WDT_EXT_RST_CTL_RST_CNT  ((uint32)0xffffU << 0U)
#define FV_WDT_EXT_RST_CTL_RST_CNT(v) \
  (((uint32)(v) << 0U) & FM_WDT_EXT_RST_CTL_RST_CNT)
#define GFV_WDT_EXT_RST_CTL_RST_CNT(v) \
  (((uint32)(v) & FM_WDT_EXT_RST_CTL_RST_CNT) >> 0U)

#define WDT_CNT_OFF  0x1cU

#define FM_WDT_CNT_WDT_CNT  ((uint32)0xffffffffU << 0U)
#define FV_WDT_CNT_WDT_CNT(v) \
  (((uint32)(v) << 0U) & FM_WDT_CNT_WDT_CNT)
#define GFV_WDT_CNT_WDT_CNT(v) \
  (((uint32)(v) & FM_WDT_CNT_WDT_CNT) >> 0U)

#define WDT_TSW_OFF  0x20U

#define FM_WDT_TSW_TSW  ((uint32)0xffffffffU << 0U)
#define FV_WDT_TSW_TSW(v) \
  (((uint32)(v) << 0U) & FM_WDT_TSW_TSW)
#define GFV_WDT_TSW_TSW(v) \
  (((uint32)(v) & FM_WDT_TSW_TSW) >> 0U)

#define WDT_INT_OFF  0x24U

#define BM_WDT_INT_OVFLOW_FUNC_INT_EN  ((uint32)0x01U << 11U)

#define BM_WDT_INT_ILL_SEQ_REFR_FUNC_INT_EN  ((uint32)0x01U << 10U)

#define BM_WDT_INT_ILL_WIN_REFR_FUNC_INT_EN  ((uint32)0x01U << 9U)

#define BM_WDT_INT_OVFLOW_INT_CLR  ((uint32)0x01U << 8U)

#define BM_WDT_INT_ILL_SEQ_REFR_INT_CLR  ((uint32)0x01U << 7U)

#define BM_WDT_INT_ILL_WIN_REFR_INT_CLR  ((uint32)0x01U << 6U)

#define BM_WDT_INT_OVFLOW_INT_STA  ((uint32)0x01U << 5U)

#define BM_WDT_INT_ILL_SEQ_REFR_INT_STA  ((uint32)0x01U << 4U)

#define BM_WDT_INT_ILL_WIN_REFR_INT_STA  ((uint32)0x01U << 3U)

#define BM_WDT_INT_OVFLOW_UNCOR_INT_EN  ((uint32)0x01U << 2U)

#define BM_WDT_INT_ILL_SEQ_REFR_UNCOR_INT_EN  ((uint32)0x01U << 1U)

#define BM_WDT_INT_ILL_WIN_REFR_UNCOR_INT_EN  ((uint32)0x01U << 0U)

#define RST_REQ_MON_OFF  0x28U

#define BM_RST_REQ_MON_INT_RST_REQ_REC  ((uint32)0x01U << 2U)

#define BM_RST_REQ_MON_INT_RST_REQ_MON  ((uint32)0x01U << 0U)

#define DUMMY_RES_OFF  0x2cU

#define FM_DUMMY_RES_DUMMY  ((uint32)0xffffffffU << 0U)
#define FV_DUMMY_RES_DUMMY(v) \
  (((uint32)(v) << 0U) & FM_DUMMY_RES_DUMMY)
#define GFV_DUMMY_RES_DUMMY(v) \
  (((uint32)(v) & FM_DUMMY_RES_DUMMY) >> 0U)

#define WDT_LOCK_OFF  0x40U

#define BM_WDT_LOCK_CLK_SRC_LOCK  ((uint32)0x01U << 6U)

#define BM_WDT_LOCK_INT_LOCK  ((uint32)0x01U << 5U)

#define BM_WDT_LOCK_EXT_RST_LOCK  ((uint32)0x01U << 4U)

#define BM_WDT_LOCK_RST_LOCK  ((uint32)0x01U << 3U)

#define BM_WDT_LOCK_WRC_LOCK  ((uint32)0x01U << 2U)

#define BM_WDT_LOCK_WTC_LOCK  ((uint32)0x01U << 1U)

#define BM_WDT_LOCK_CTL_LOCK  ((uint32)0x01U << 0U)

#define WDT_ERR_INJ_EN_OFF  0x4cU

#define BM_WDT_ERR_INJ_EN_OUT_INJ_EN  ((uint32)0x01U << 2U)

#define BM_WDT_ERR_INJ_EN_IRQ_INJ_EN  ((uint32)0x01U << 1U)

#define BM_WDT_ERR_INJ_EN_APB_INJ_EN  ((uint32)0x01U << 0U)

#define WDAT_ERR_INJ_OFF(n)  (0x50U + 4U*(n))

#define WECC_ERR_INJ_OFF(n)  (0x54U + 4U*(n))

#define APB_ERR_INT_OFF(n)  (0x58U + 4U*(n))

#define WDT_FUSA_INT_OFF  0x5cU

#define BM_WDT_FUSA_INT_SYNC_ERR_CLR  ((uint32)0x01U << 16U)

#define BM_WDT_FUSA_INT_SYNC_ERR_STA  ((uint32)0x01U << 8U)

#define BM_WDT_FUSA_INT_SYNC_ERR_EN  ((uint32)0x01U << 0U)

#define WDT_ERR_INJ_OFF(n)  (0x60U + 4U*(n))

#define BM_WDT_ERR_INJ_EXT_RST_REQ_INJ  ((uint32)0x01U << 4U)

#define BM_WDT_ERR_INJ_INT_RST_REQ_INJ  ((uint32)0x01U << 3U)

#define BM_WDT_ERR_INJ_UNC_IRQ_INJ  ((uint32)0x01U << 2U)

#define BM_WDT_ERR_INJ_COR_IRQ_INJ  ((uint32)0x01U << 1U)

#define BM_WDT_ERR_INJ_WDT_IRQ_INJ  ((uint32)0x01U << 0U)

#define PRDATAINJ_OFF  0x70U

#define REG_PARITY_ERR_INT_STAT_OFF  0x74U

#define REG_PARITY_ERR_INT_SIG_EN_OFF  0x78U


#endif   /* __WDT_REG_H__ */
/* End of file */
